The present invention relates generally to an integrated circuit (IC) design, and more particularly to a system of a dynamic power control circuit implemented to an array of SRAM devices for improving write margin.
In deep sub-micron technology, an embedded SRAM has become a very popular storage unit for high-speed communication devices, image processing devices, and other system-on-chip (SOC) products. For a typical SRAM cell, one of the most important aspects is the stability of the cell. The write margin of a SRAM cell is one of the key factors that determine the stability of the device. As data is programmed within a SRAM cell, a large write margin can improve the writing speed and ensure that the correct data is being written.
Several attempts have been made in the past to improve and expand the write margin of a SRAM cell. One of such attempts floats power supplies to a cell array being accessed during a write cycle. However, this may result in lowering writing speeds and even degrading data retentions.
Another attempt utilizes two different power supplies, and a lower voltage is supplied to the cell array during write operations. However, implementing two power supplies within an embedded IC is difficult and will significantly increase the die size of such IC.
Desirable in the art of SRAM designs are circuits that improve the write margin without degrading the data retention or increasing the die size.